QUASAR-CREATE · Thrust 1Open and Verifiable Secure RISC-V Processor PlatformPost Quantum Cryptography & Hardware Security
Developing an open and verifiable RISC-V processor platform as a future trust anchor. Integrating PQC accelerators, side-channel-resistant hardware, secure key storage, and a hardened operating system to build quantum-safe hardware systems. This thrust sets a special focus on open-source hardware and software tool utilization for security, verification, and supply-chain resilience.
RISC-V Security · Hardware-Software Co-Design · Open Source EDA · Post-Quantum Accelerators
Research in Quantum Safe Cryptographic Hardware
Hardware is the foundation of trust. Secure, verifiable systems start at the silicon level.
As we migrate to post-quantum cryptography, the hardware running these new algorithms must be resilient against both quantum attacks and physical side-channel vulnerabilities. Thrust 1 focuses on resource-efficient, performance-optimized solutions for quantum computer attack-resistant systems-on-chip (SoC) and HW/SW co-design. A special focus is placed on RISC-V design, open-source hardware, open software tool utilization for security and verification, supply-chain resilience, and capacity building.
From Open Source Hardware Design to Open Silicon
Verifiable Secure System on Chip Architecture
Thrust 1 engineers a 64-bit RISC-V secure processor platform with tightly integrated PQC/QKD features and secure key handling.
Secure SoC Architecture
- OpenTitan Secure Element
- CVA6 based Secure Processor
- PQC Accelerators
- Symmetric Crypto Co-processors
- Secure OS Integration
- HW/SW Co-Design Tooling
Research Areas
Five focused working areas driving the development of the open and verifiable secure RISC-V processor platform.
Design of an Open & Verifiable Secure Platform
Developing a secure 64-bit RISC-V system-on-chip (SoC) architecture, integrating OpenTitan secure elements, memory, and peripherals, establishing a foundation for verifiable trust.
Key Outputs
- →64-bit RISC-V Secure Processor
- →OpenTitan Integration
- →System-on-Chip (SoC) Architecture
Chip Design with Open-Source IC Design Software
Taping out complex SoCs using open-source tools in an open process design kit, demonstrating supply-chain resilience and fostering capacity building in the local ecosystem.
Key Outputs
- →Open-source EDA toolchains
- →Open Process Design Kit (PDK)
- →Capacity building
PQC Accelerators & Design Space Exploration
Researching the best resource-efficient and performance-optimized HW/SW co-design solutions for new PQC algorithms of the NIST call.
Key Outputs
- →PQC HW/SW co-design
- →Resource efficiency optimization
- →Integration tooling
Side-Channel-Resistant Symmetric Crypto
Designing symmetric cryptographic accelerators that are inherently hardened against advanced side-channel and fault injection attacks.
Key Outputs
- →Side-channel resistance
- →Fault attack hardening
- →Secure key handling
Physcial Unclonable Functions and Secure Boot
To enable a secure root of trust, we integrate physically unclonable functions (PUFs) with secure boot mechanisms, creating tamper-evident hardware that ensures system integrity from power-on.
Key Outputs
- →Physical Unclonable Functions (PUFs)
- →Secure Boot Mechanisms
- →Tamper-Evident Hardware
Secure Operating System Gyroid OS
Investigating hardware features that increase the security of an open-source secure OS.
Key Outputs
- →Hardware-OS Codesign
- →Isolated Execution Environments
- →Fraunhofer AISEC GyroidOS
QUASAR-CREATE · Thrust 1
Prototyping Quantum-Safe Silicon
The RISC-V Hardware Demonstrator
Validating our architectures through a progressive pipeline: from Virtual Prototypes to FPGA basis boards, culminating in an ASIC demonstrator.
Our hardware development pipeline ensures rigorous testing at every stage. We utilize virtual prototyping for early software development and architectural exploration, deploy to FPGA basis boards for high-speed emulation, and aiming to finalize the design in a physical ASIC tapeout.
Virtual Prototyping
Software models of the hardware architecture that allow the team to begin Secure OS integration and HW/SW codesign optimization long before physical silicon is available.
FPGA Proof of Concept
Physical FPGA deployments to validate side-channel resistance, memory bottlenecks, and interconnect performance in a realistic real-time environment.
ASIC Demonstrator
The final physical chip, fabricated using an open process design kit. This demonstrator proves the viability of using open-source EDA tools for complex, secure system-on-chip designs.
Research Team
Principal investigators and researchers from the QUASAR-CREATE consortium driving open and verifiable secure RISC-V processor platform development.
Georg Sigl
Professor, Programme Lead-PI
Technical University Munich (TUM)
Gwee Bah Hwee
Professor, Principal Investigator
Nanyang Technological University (NTU)
Ulf Schlichtmann
Professor, Principal Investigator
Technical University of Munich (TUM)
Michael Pehl
Professor, Principal Investigator
Technical University of Munich (TUM)
Zhidan Zheng
Coordinator, Thrust 1
TUM CREATE
Juncheng Chen
Research Fellow, Thrust 1
NANYANG TECHNOLOGICAL UNIVERSITY (NTU)
Liu Shukun
PhD Student, Thrust 1
NANYANG TECHNOLOGICAL UNIVERSITY (NTU)
Jeng-De Chang
Research Engineer, Thrust 1
TUM CREATE
Collaborate with Us on Quantum-Safe Hardware and Open Source Design
Thrust 1 works with security researchers and the open-source EDA community to build verifiable, post-quantum resilient silicon.
Hardware
Architecture
Design collaboration on open and verifiable RISC-V platforms.
Join the
Team
Explore job opportunities and PhD positions in our group.
Research Collaboration
Joint projects, and publication collaboration on HW/SW codesign.
Capacity
Building
Leverage open-source EDA tools and training programmes.